1. Field of the Invention
The present invention relates to a wiring layout method and a computer readable medium storing a program executed by a computer to execute the layout method.
2. Description of the Related Art
In recent years, integrated circuits are becoming smaller and smaller in size and coming to use higher and higher signal frequencies. Under such circumstances, the wirings of those integrated circuits are also becoming thinner and thinner. If wirings are becoming thinner and thinner in such a way, forming a capacitance comes to be required between multilayer wirings. Then, the wiring capacitance causes the signal delay time to be extended significantly. In order to suppress such extension of the signal delay time caused by the wiring capacitance, there have been some techniques developed to reduce the wiring capacitance. One of such techniques, which is widely known, uses a low dielectric constant film as an insulation film provided between wiring layers. When compared with the conventional oxide film used as interlayer films, the low dielectric constant film is generally low in thermal conductivity. When designing an integrated circuit, therefore, it becomes very important to take consideration to how to lower the heat generated from each wiring layer.
A current, when it flows in a wiring of an integrated circuit, comes to cause Joule's heat generation. If the temperature of the wiring rises excessively due to the Joule's heat generation, it results in lowering the reliability of the integrated circuit itself. This is why, when designing an integrated circuit, it is required to determine the wiring layout so as to suppress the influence of the Joule's heat generation effectively.
As a known technique for suppressing the Joule's heat generation, JP-A Hei8 (1996)-6980 (patent document 1) discloses “a power consumption estimating method”.
This invention is intended to estimate wiring power consumption quickly and accurately using a prepared test pattern and without executing any simulations. In other words, the power consumption of a target wiring is calculated by a formula on the basis of a probability that the status of each input/output signal flowing in the target signal wiring might change (the probability denotes that a signal status changes to 0 or 1 and it is equivalent to a concept that the probability is equivalent to the frequency f of the subject signal flowing in the signal wiring).
In the known patent document 1, the current consumption I of the wiring capacitance C is focused and the power consumption of the target integrated circuit is estimated with use of a formula. Generally, the current consumption In of a signal wiring n is calculated as In=Cn×V×fn by using the wiring capacitance Cn of the signal wiring n, the signal voltage V, and the signal frequency fn.
In this case, however, the voltage V is premised to be a fixed value. Consequently, the higher the probability that the input/output signal changes from 0 to 1 or from 1 to 0, the larger the current consumption I of the wiring capacitance C becomes, thereby the power consumption of the integrated circuit comes to increase.
The present inventors have recognized that the patent document 1 has the following problem.
If the power consumption of an integrated circuit is evaluated excessively, it comes to be required to widen the wiring width and secure a wider wiring pitch unnecessarily. This requires a wider area for the integrated circuit. This problem can be avoided, however, by taking consideration to various factors to prevent such excessive evaluation when evaluating a temperature rise to be caused by the Joule's heat generation in a designing process of the integrated circuit. In spite of this, if an attempt is made to estimate the power consumption of an integrated circuit by evaluating all of the wirings just like in the patent document 1, power consumption calculation is also required for each wiring of which temperature will not rise actually. This means that the power consumption of the integrated circuit in the patent document 1 is apt to be estimated excessively.